STLS2F Loongson 2F high performance bit superscalar MIPS. ® microprocessor. Features. □ bit superscalar architecture. □ MHz clock frequency. Loongson 2F: High performance bit superscalar MIPS. ® microprocessor. Features. □ bit superscalar architecture. □ MHz clock. ICT Loongson 2F (ST STLS2F01) (Godson-2). ICT Loongson 2F ( MHz) (90 nm) + MB of DDR2. Lemote YeeLoong notebook. 4-way superscalar.
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It is fabricated with 0. Instructions are executed according to its type and execution results are written back to the register file.
Result buses are also sent to the reservation station for snooping and to the register mapping table to notify that the associated physical register is ready. This desktop solution uses an optimized version of Fedora 13, with a lot of software ported and available, such as Kingsoft WPS office suite.
Each loongskn can be clocked from 1. Associated instructions are also sent to branch queue and memory queue. For the performance, because the frequency is only 1. The manufacturer states that loongso user experience of the desktop solution has been significantly improved over its Loongson-3A based predecessor. Most common open-source applications including OpenOffice. June Learn how and lopngson to remove this template message. Inter-instruction dependencies among four instructions mapped in the same cycle are also checked.
Archived from the original on 23 October Retrieved 26 May Committed instructions are sent to the register mapping module to confirm the mapping of its destination register and release the old one.
Retrieved 31 May Loongson is the result of a public—private partnership. Four new instructions are sent to the instruction register IR if the instruction fetch is a TLB hit and a loongskn hit.
The topic of the speech was “Research and Development of Godson processors”. China enters the low-cost laptop competition. It was formerly called Godson.
Debian — Details of package linux-image-loongson-2f in jessie
Archived from the original on 4 June This page was last edited on 2 Decemberat Tag compare is also performed at this stage, but value selection according to tag compare result is delayed to next cycle.
Each empty entry of reservation stations and queues selects among four dispatched instructions in this cycle. In other projects Wikimedia Commons. In SeptemberLemote announced the Yeeloong It may also get the data directly from one of the result buses if its source register number matches the destination register number of the result bus.
Archived from the original on 23 April Many operating systems work on Loongson: Archived from the original on 25 July This article’s use of external links may not follow Wikipedia’s policies or guidelines.
Loongson 2F 900MHz vs MediaTek MT8163 V/A 1.5 GHz
Marvell 88E “Link Street”. The Loongson 2 adds bit ability to the Loongson architecture. Archived from the original on 17 April The value is then sent to memory access queue, where dynamic memory disambiguation and memory forwarding is performed. Open source applications on Linux Platform can be ported with little effort.
InLoongson released latest version of 3A cpu, 3A They are also sent to the memory access queue to allow committed store instructions to write cache or memory. Wikinews has related news: Archived from the original on 15 September Archived from the original on 9 May The high-performance Dawningwhich has a projected speed of over one quadrillion operations per second, will incorporate the Loongson processor as its core.
Archived from the original on